The present invention relates to carbon nanotube transistors and, in particular, to methods for reducing device OFF current and increasing the performance of carbon nanotube transistors.
Thin-film transistors are commonly used in display technologies, such as liquid crystal displays (LCD). Carbon nanotube thin-film transistors have the potential to replace standard thin-film transistors that are based on amorphous silicon or poly-silicon material. These transistors generally have higher mobility than Si-based thin-film transistors and can be fabricated with lower cost. The capability of depositing carbon nanotube thin film at room temperature allows the device fabrication on flexible substrates, enabling other new applications such as flexible electronics and displays. One important device performance parameter is the ratio between ON source-drain current (where both gate-source and drain-source biases are at full bias) and OFF source-drain current (where drain-source is at full bias and gate-source is at zero bias). Despite the abovementioned advantages of using carbon nanotube thin-film material, transistors with this material potentially suffer from larger OFF current due to Schottky barrier contacts. The ambipolar current from the thermionic emission over the Schottky barrier height greatly limits device ON/OFF ratio, in particular with a larger voltage applied between the source and the drain. Thus, improving ON/OFF ratios of carbon nanotube thin-film transistors is desired.